The present invention relates generally to signal delay devices, and in particular to digital delay elements that are programmable for use with computer system components.
As the operation speed of computer systems continues to increase, the need exists to delay either clock or data signals to optimize the critical timing within the computer system due to the timing requirements of system components. Certainly, as the clock rate in the system increases, timing between the computer elements and within the computer chips becomes critical. One method to control the timing has been with a delay elements controllable through a digital Delay Locked Loop (“DLL”). These devices have been typically limited to coarse variable-delays where the incremental delay unit is one or two logic gates providing one or two blocked delay units, accordingly. Additionally, these devices could not be used to generate multiple delayed signals without including a DLL in each clock domain and doing so would result in large circuit overhead.
A design consideration for a delay element is its delay resolution and its insertion delay. The delay resolution is the unit of delay available through a delay element. Conventional delay circuits with blocked unit delays may be acceptable for low frequency operation, but high performance circuits require fractional increments of blocked delays. Insertion delay is the amount of delay generated by a delay element when at a zero delay state. The insertion delay is an important consideration particularly when deskewing data, since any added delay in a data path decreases overall performance.
Accordingly, a need exists for a programmable delay element for high performance computer systems that has greater delay resolution and negligible insertion delay. Also since different portions of a circuit can require different amounts of delay in the clock, a signal generation and distribution circuit is needed that is designed to accommodate multiple configurable and flexible delay requirements while maintaining a high degree of accuracy and minimizing circuit overhead.